When developing an integrated circuit (“IC”), particularly a complex integrated circuit such as some application specific integrated circuits (“ASICs”), several development stages are implemented. Typically, the integrated circuit is designed at a high, functional level using a behavioral language, such as Verilog or VHDL. Typically, smaller portions of the IC are designed as a functional unit, called an island. For example, the random access memory (“RAM”) might be one island in a particular IC that is designed using a behavioral language. The design phase also typically includes compiling the code for each of the islands. Once the design of the islands for the IC has been completed, a simulation phase is entered. In the simulation phase, each of the islands is tested. When testing of the islands is completed, the islands are integrated together. When the entire IC has been integrated, the entire design is simulated and verified. Upon completion, the integrated simulation phase is completed. Once the simulation phase is completed, a synthesis phase is entered. In the synthesis phase, the tested, integrated design is converted to logical gates. These gates can then be converted into a specific technology, using design rules. These design rules are used to physically layout structures on the dies in the physical design stage of development.
FIG. 1 depicts one embodiment of an IC 10 that is designed using a behavioral language. The IC 10 includes islands 12, 14, 16, 18, 20 and 22. The IC 10 also includes external interfaces 24, 26 and 28 through which signals can be input to or output from the IC 10. The islands 12, 14, 16, 18, 20 and 22 are connected to each other through internal interfaces 30, 32, 34, 36, 38, and 40.
The IC 10 is hierarchical in design. The islands 12, 14, 16, 18, 20 and 22 are at a lower level in the hierarchy because the islands 12, 14, 16, 18, 20 and 22 are simpler and function as a unit. Some of the islands 12, 14, 16, 18, 20 and 22 can be stitched together, or integrated, to form a set of islands. Sets of islands form the next level in the hierarchy. Typically, a set in this level of the hierarchy is formed by pointing to the island 12, 14, 16, 18, 20 or 22 which belongs to the set. Sets of islands can be integrated to form the next level in the hierarchy of the IC 10. This level of the hierarchy typically points to sets of islands. The hierarchy continues to higher levels, forming the IC 10.
FIG. 2A depicts one embodiment of a conventional method 50 for performing the simulation phase of development for the IC 10. Thus, the conventional method 50 typically commences after individual islands 12, 14, 16, 18, 20 and 22 have been coded using a hierarchical design language and compiled in a design phase. Simulation for the IC 10 exploits the hierarchical nature of the IC 10. The conventional test cases and conventional models for testing of individual islands 12, 14, 16, 18, 20 and 22 are provided, via step 52. The individual islands 12, 14, 16, 18, 20 and 22 are then tested using the conventional test cases and models for each of the islands, via step 54. The conventional test cases and models provide a simulation environment for each of the islands 12, 14, 16, 18, 20 and 22. Thus, the conventional test cases and models provided data to each of the islands 12, 14, 16, 18, 20 and 22 and check the output of each of the islands 12, 14, 16, 18, 20 and 22. Because each island 12, 14, 16, 18, 20 and 22 is relatively simple, the testing of each island 12, 14, 16, 18, 20 and 22 can be relatively exhaustive. Step 54 continues until each of the islands 12, 14, 16, 18, 20 and 22 function.
The next level in the hierarchy is then built by integrating the level that has completed testing, via step 56. Since the level in the hierarchy that has completed testing is the islands 12, 14, 16, 18, 20 and 22, step 56 includes integrating some of the islands may be integrated into sets. Step 56, therefore, allows some of the islands to be stitched together to form a set. Thus, a new level in the hierarchy is formed. A new set of conventional test cases and models are then provided for the level of the hierarchy just formed, via step 58. Consequently, conventional test cases and conventional models are provided for each set of integrated islands in step 58. These conventional test cases and models provide a simulation environment for the newest level being tested. The newest level of the hierarchy, the integrated islands, are then tested using the new conventional test cases and models, via step 60. It is then determined whether integration is complete, via step 62. If so, then the simulation process is completed. If not, steps 56 through 62 are repeated. Thus, a new level in the hierarchy is formed by stitching the sets of islands together. New conventional test cases and models are provided and the new level in the hierarchy tested. This process of integrating portions of the current level of the hierarchy of the IC 10 to form a new level, providing test cases and models, and testing the new level is repeated until simulation of the entire IC 10 is completed.
FIG. 2B depicts the island 12 during initial testing in step 54. The conventional models 70, 72, 74 and 76 as well as the corresponding conventional test cases 71, 73, 75 and 77 have been provided. Like the islands 12, 14, 16, 18, 20 and 22, the conventional models 70, 72, 74 and 76 are compiled code. The conventional models 70, 72, 74 and 76 are preferably written in the same code as are the islands 12, 14, 16, 18, 20 and 22. The conventional models 70, 72, 74 and 76 couple to the appropriate island 12 and provide data to and receive output from the island 12. Similar conventional test cases and models (not shown) are used to individually check the other islands 14, 16, 18, 20 and 22. The conventional test cases 71, 73, 75 and 77 include data which are input to the islands by the conventional models 70, 72, 74 and 76. In addition, the conventional test cases 71, 73, 75 and 77 include sufficient intelligence to control the conventional models 72, 74, 76 and 78 during testing. For example, a conventional test case 71, 73, 75 and 77 may tell a conventional model 72, 74, 76 and 78 to input data to an island 12, wait for an output from the island 12, check the output received from the island 12 against an expected output, and flag an error if the output does not match the expected output. Thus, the conventional test cases 71, 73, 75 and 77 are relatively complex, while the conventional models 72, 74, 76 and 78 are relatively simple. The conventional test case 71, 73, 75 or 77 may also have several different permutations of the data to be input to the island 12. Therefore, although only one test case 71, 73, 75 or 77 is shown for each model 70, 72, 74 or 76, there may be numerous test cases for each model 70, 72, 74, or 76.
FIG. 2C depicts the islands 12, 14, and 16 after they have been integrated in step 56. New conventional models 80, 82, 84, 86, and 88 and new conventional test cases 81, 83, 85, 87 and 89 have been provided. Thus, the conventional models 80, 82, 84, 86, and 88 and conventional test cases 81, 83, 85, 87 and 89 are used for testing the set of islands including the islands 12, 14 and 16. The conventional models 80, 82, 84, 86, and 88 are preferably written in the same code as are the islands 12, 14, 16, 18, 20 and 22. The conventional models 80, 82, 84, 86, and 88 couple to the appropriate islands 12,14 and 16 and provide data to and receive output from the islands 12, 14 and 16. Other test cases (not shown) are used for other sets of islands. The conventional test cases 81, 83, 85, 87, and 89 include data which are input to the islands by the conventional models 80, 82, 84, 86, and 88. In addition, the conventional test cases 81, 83, 85, 87, and 89 include sufficient intelligence to control the conventional models 80, 82, 84, 86, and 88, respectively during testing. The conventional test cases 81, 83, 85, 87, and 89 may also have several different permutations of the data to be input to the island 12. Thus, the conventional test cases 81, 83, 85, 87, and 89 are relatively complex, while the conventional models 82, 84, 86, and 88 are relatively simple. The conventional test cases 81, 83, 85, 87, and 89 may also have several different permutations of the data to be input to the island 12. Therefore, although only one test case 81, 83, 85, 87, or 89 is shown for each model 80, 82, 84, 86, or 88 there may be numerous test cases for each model 80, 82, 84, 86, or 88.
FIG. 2D depicts the IC 10 just before the last round of testing is completed in step 60. Conventional models 90, 92 and 94 and conventional test cases 91, 93 and 95 are coupled to the external outputs 24, 26 and 28 of the IC 10. Thus, the conventional models 90, 92 and 94 and conventional test cases 91, 93 and 95 are used for testing the IC 10. The conventional models 90, 92 and 94 are preferably written in the same code as are the islands 12, 14, 16, 18, 20 and 22. The conventional models 90, 92, and 94 couple to the appropriate islands 16, 14 and 20 and provide data to and receive output from the islands 16, 14 and 20. The conventional test cases 91, 93 and 95 include data which are input to the islands by the conventional models 90, 92 and 94, respectively. In addition, the conventional test cases 91, 93 and 95 include sufficient intelligence to control the conventional models 90, 92 and 94, respectively, during testing. Thus, the conventional test cases 91, 93 and 95 are relatively complex, while the conventional models 90, 92 and 94 are relatively simple. The conventional test cases 91, 93 and 95 may also have several different permutations of the data to be input to the island 12. Therefore, although only one test case 91, 93 or 95 is shown for each model 90, 92, or 94 there may be numerous test cases for each model 90, 92 or 94. Thus, the conventional models 90, 92, and 94 are used in testing the highest level of the hierarchy for the IC 10. The models 90, 92 and 94 provide inputs to the IC 10, and check the outputs from the IC 10 to ensure that the IC 10 functions as desired. Once testing of this level is completed, the simulation phase of development is complete.
Although the simulation phase can be performed using the method 50 and conventional test cases and models, one of ordinary skill in the art will readily recognize that there are a number of drawbacks to using the method 50 and conventional models and test cases. Simulation typically takes place relatively close to the end of development. However, in order to complete simulation using the method 50, new conventional test cases and models are generated for each level of the hierarchy that is constructed. Thus, conventional test cases and models are provided for the individual islands as well as for sets of islands and groups of sets of islands. Thus, a large number of conventional test cases and models is needed for simulation. Furthermore, numerous conventional test cases, which are relatively difficult to construct, are required for each level in the hierarchy. Providing such a large number of conventional test cases and models islands consumes a significant amount of manpower and other resources near the date on which the IC 10 is to be completed.
Furthermore, one of ordinary skill in the art would readily realize that the conventional models are coupled to the islands at an external interface. For example, in FIG. 2C, only conventional models 84 and 86 are coupled to the island 14. During testing, the model 84 may provide an input to the island 14. The island 14 may process the input, provide an output to the island 12, receive a second input back from the island 12 and provide a second output back to the conventional model 84. The conventional model 84 only has information about the original input and the second output. The conventional model 84 can thus only check the second output. The conventional model 84 cannot check information and diagnose failures at the interface 30 between the island 12 and the island 14. Thus, conventional test cases and models are limited in their ability to test the internal workings of the IC 10 at the hierarchical level being tested.
Accordingly, what is needed is a system and method for performing a more efficient and more accurate simulation phase in IC development. The present invention addresses such a need.